Shahriar Mirabbasi

Professor

Relevant Degree Programs

 

Graduate Student Supervision

Doctoral Student Supervision (Jan 2008 - Mar 2019)
Radio frequency CMOS : from ultra-high speed to ultra-low power (2018)

Over the last three decades, radio-frequency(RF) Complementary Metal-Oxide-Semiconductor(CMOS) electronics has made a huge impact in our world. Wireless Local Area Networks(WLANs), cellular networks, Global Positioning Systems(GPSs), and Bluetooth are a few examples where the impact of RF CMOS has led to rapid adoption and standardization of the technology. However, there still exists several challenging areas at the intersection of RF and CMOS where new paradigms must be established. This thesis summarizes the research to meet those goals as briefly described here: Research during the past decades provided CMOS solutions to RF applications that utilize the frequency spectrum up to 6 GHz. However, efficient system integration of mm-wave and THz in CMOS is still a challenging task. The THz spectrum is gaining interest due to its wider and less populated available spectrum, as well as its intriguing applications in molecular spectroscopy, imaging, and sensing. This band, although very useful, has been difficult to realize in hardware because of the limitations in CMOS electronics. In the first four chapters of this thesis, we investigate the challenge of implementing signal-sources at mm-wave and sub-THz frequencies using low-cost and versatile CMOS circuits, replacing the existing expensive solutions.Demand for embedded low-power electronics for wireless connectivity is growing due to the rapid proliferation of Internet-of-Things (IoT). Although Wireless Sensor Network(WSN) had been around for decades, some applications such as biomedical monitoring systems require ultra-low-power(ULP) and cost-effective wireless solutions. Research on energy-harvesting systems (e.g., RF energy harvesting, thermoelectric, etc.) and integrated-circuits(IC) bears the promise of medium-reach battery-free wireless connectivity solutions. In Chapters 5 and 6 of this thesis, multiple ULP wireless connectivity solutions for both commercial standards such as Bluetooth Low Energy(BLE) and custom-designed application-specific-radios are proposed and implemented in 40nm and 130nm CMOS technologies, respectively.Finally, application of RF electronics in power-electronics is studied in the last chapter. Although power-management integrated circuit is a well-developed field of research, PMICs still have existing bottlenecks (e.g., die area and output ripple) which can be addressed with the knowledge of RF electronics. In this thesis, feasibility of GHz-range converters is studied.

View record

Analysis and design of analog interface circuits for capacitive detector readout systems (2017)

Advances in sub-micron complimentary metal-oxide semiconductor (CMOS) technologies have enabled implementation of ultra-low-power circuits and systems for variety of applications including readout systems for capacitive radiation detectors. As state-of-the-art readout systems may integrate thousands of electronic channels on chip, designing low-power and low-noise interface circuits is of great interest. The focus of this work is on developing a design methodology for such readout circuits with an emphasis on interfacing with capacitive sensors, in general, and solid-state radiation detectors, in particular. The critical aspects of the design from analyzing the specifications to noise optimization and circuit design are taken into account and the proposed circuits offer improved performance for the readout system.To facilitate the noise analysis of modern readout systems, the equivalent noise charge equations of the system are derived analytically. The analysis takes into account the stringent requirements of modern readout systems as well as the noise sources associated with deep submicron CMOS technologies. The analysis is based on the EKV (Enz, Krummenacher, and Vittoz) model of MOS transistors which is a model valid for all regions of operation.As a proof of concept, the analysis and design of three low-power and low-noise interface circuits are presented. The proposed circuits are fabricated in a 0.13 um CMOS process. The first interface circuit consists of a novel charge-sensitive amplifier (CSA), a pole-zero cancellation (PZC) circuit, and a 2nd-order programmable pulse shaper. The proposed CSA accepts signals of both polarities, exhibits 111 e-rms noise, and consumes only 37.5 uW. The second interface circuit consists of a CSA, a reset network, a 1st-order shaper, and a PZC circuit. The circuit consumes about 1 mW and exhibits 66 to 101 e-rms noise at different peaking times. The third interface circuit is a mixed-signal design and consists of a CSA with leakage compensation, a 5th-order programmable Gaussian shaper, a peak-detect and hold, a discriminator, and a novel Wilkinson-based digitizer. The circuit consumes 1.97 mW and exhibits 58 e-rms noise. The design performs favourably in terms of power consumption and noise behavior in comparison with similar works in the literature.

View record

On the electronic-photonic integrated circuit design automation : modelling, design, analysis, and simulation (2017)

Photonic networks form the backbone of the data communication infrastructure. In particular, in current and future wireless communication systems, photonic networks are becoming increasingly popular for data distribution between the central office and the remote antenna units at base stations. As wireless-photonic systems become increasingly more popular, not only low-cost implementation of such systems is desirable, but also a reliable electronic-photonic design automation (EPDA) framework supporting such complex circuits and systems is crucial. This work investigates the foundation and presents implementation of various aspects of such EPDA framework. Various building blocks of silicon-photonic systems are reviewed in the first chapter of the thesis. The review discusses an example of a 60-GHz wireless system based on photonic technology, which could be suitable for the emerging 5th-generation (5G) cellular networks, and also provides design use cases that need to be supported by the EPDA framework.Integrated photonic circuits, which are the building blocks of wireless-photonic systems, will achieve their potential only if designers can efficiently and reliably design, model, simulate, and tune the performance of electro-optical components. The developed EPDA framework supports an integrated optical solver, INTERCONNECT, to provide optical time and frequency domain simulations so that a designer would be able to simulate electrical, optical, and electro-optical circuits using two developed and implemented methodologies: sequential electro-optical simulation and co-simulation. We propose an algorithm to enhance the performance of electronic simulation engines that can be integrated into the EPDA simulation methods such as Harmonic Balance. It will be shown that body-biasing of CMOS transistors can be used as an effective method for tuning the performance of the electronic section of an electro-optical design. This can help designers adjusting the performance of their designs after fabrication. Modelling of electro-optical components is discussed in this thesis; It is shown that some traditional passive components such as inductors, which take a large amount of space in CMOS processes, could be fabricated in the much lower cost photonic process and consequently the overall cost of silicon-photonic systems can be reduced significantly.

View record

Design techniques for low-power low-noise CMOS capacitive-sensor readout circuits (2015)

In recent years, the demand for low-cost, high performance, and miniature sized MEMS capacitive inertial sensors (accelerometer/gyroscope) has been steadily increasing. Use MEMS capacitive accelerometer as an example, for high precision applications, the resolution needs to be in the μg range at the frequency of interest. These high performance sensors are now been used in numerous applications that require more demanding specifications. For instance, they found their use in active suspension, adaptive brakes, alarm systems, tilt control, vibration, shock measurements, platform stabilization, inertial measurement units, inertial navigation/guidance, machine control, microgravity measurements, seismology, geophysical sensing, oil-field applications, earthquake detection, tactical missiles, robotics and minimally invasive surgery.The precision in a micro-sensory system is limited by the CMOS electronic interfaces, due to the often higher electrical noise associated with the circuits. Additionally, with the growing popularity for portable devices such as cellular phones and tablets, power consumption also becomes an important factor. Therefore, the dissertation discusses and presents several circuit design techniques that improve important system parameters such as noise and power. Moreover, a design flow is provided at the end of the thesis to demonstrate a systematic approach to design the sensor interface circuits. Three major readout circuit blocks have been designed, built, and tested. The first interface uses a circuit technique such that the overall system is insensitive to parasitic capacitances from the sensing nodes. Moreover, a calibration scheme is used to remove DC offset caused by sensor capacitance mismatch. The second interface uses two circuit design techniques called correlated level shifting (CLS) and chopper stabilization (CS) to reduce the noise and the finite gain error from the operational amplifier (op amp), thereby improving both the noise and power performance of the system. The final interface utilizes a modified CLS technique such that it also serves as a noise and power improving mechanism. The first two readout circuits have been tested and measured experimentally, while the third readout circuit is verified via post-layout simulation.

View record

Power line communications in vehicles : channel measurements and impedance matching networks (2015)

In today's Electric Vehicles (EVs) and conventional Combustion Engine Vehicles(CEVs), data communication between electronic control units is accomplished by sending communication signals over dedicated wires. The space requirement, weight, and installation costs for these wires can become significant, especially in electric vehicles of the future, which are highly sophisticated electronic systems. This has motivated research and development activities in the area of Vehicular Power Line Communication (VPLC). VPLC systems reuse power wires inside a vehicle for data communicationpurposes. Thus, they eliminate the need for extra wires dedicated to communication.However, there are several impediments to overcome in order to achieve a reliable and robust VPLC. Many of these challenges originate from inherentproperties of current wirings in vehicles, which are not designed with communication in mind. Therefore, to develop suitable data transmissionequipments, a good understanding of the communication channel characteristics is essential. Considering the importance of proper characterization as a first step towards the design and deployment of VPLC systems, in this work, we have tried to contribute to the available body of knowledge on channel characterization for VPLC in EVs and CEVs. As tangible contributions, we present methodology and results of two measurement campaigns in this thesis. The main outcomes of this part of our research are quantitative statements about Channel Transfer Functions and Access Impedance for two vehicles and discussions of our results in the context of VPLC system design.Building on the results of these measurements, an adaptive impedance matching system is designed to improve the power transmission between VPLC devices and the vehicular power line network, and consequently improve the Signal-to-Noise Ratio (SNR) of the communication system. The adaptive impedance matching system is first behaviorally described in VHDL-AMS and simulated using Cadence™ and then for each unit a circuit design compatible for implementation on an Integrated Circuit (IC) platform is suggested.Tested against the challenges of VPLC observed in our measurement campaigns, the proposed system proved to be capable of significantly improving the reliability of communication over power wires in vehicle.

View record

Biomedical telemonitoring systems with an emphasis on in-stent restenosis monitoring (2014)

Advances in microelectronic technologies have facilitated implementation of leading-edge circuits particularly in the realm of ultra-low-power circuits and systems. The focus of this thesis is on the design of reliable integratedsolutions for telemonitoring of biomedical implants. In particular, we focus on diagnosing in-stent restenosis (re-narrowing) of coronary arteries after angioplasty. To achieve more efficient wireless power delivery, a modifiedversion of conventional medical stent, namely antenna stent or stentenna, is used. In this work, two different systems are designed and fabricated in a 0.13-μm complimentary metal-oxide semiconductor (CMOS) process. The first telemonitoring system converts the capacitive changes of the (pressure) sensors directly to a corresponding frequency change which will betransmitted to the external reader. Unique to this design is the alignment unit which is designed to improve the physical alignment of external inductive antenna with the implanted stentenna for the purpose of wireless power transfer. The system starts operating with the rectified voltage of as low as 500 mV while consuming 4.15 μW, 3.4 μW of which is consumed by the transmitter. The system is designed such that, in alignment mode, the frequency of the pilot signal is directly proportional to the value of the rectifiedsupply voltage. The monitoring unit, start operating from the supply voltage of 870 mV while drawing 111.25 μA. This system has been successfully tested in an in-vitro setup. The measured sensitivity of the system is 555 kHz/fF.This system is capable of detecting capacitance change of as low as 1.3 fF.The sensor interface circuit of the second system consists of a capacitance-to-voltage converter and the transmitter includes a voltage-to-frequency converter.The frequency for the transmitted signal is proportional to the changes of the capacitance of the sensor. Measurement results of a proof-of concept prototype show that the system operates from a harvested supply of as low as 350 mV (from input power of -43.76 dBm at 1.25 GHz) whiledrawing less than 100 nA from its harvested supply. The sensitivity of the system is measured to be 55 kHz/fF.

View record

Efficient power and data converter circuits for RFID applications (2014)

The basic concept of radio-frequency identification (RFID) as a means of wireless identification of physical objects has existed for over half a century. However, the technology became economically feasible during the mid-90s mainly due toproliferation of low-cost integrated circuits. Since its emergence, RFID technology has gained extensive attraction and has been used in numerous industrial applications. To facilitate widespread deployment, RFID tags as the backbone of such identification systems have to fulfil two general requirements, namely, low power consumption and small form factor. In this thesis, with an emphasis on power and area efficient architectures, efficient data and power converters as the two major building blocks of sensor-enabled RFID tags are investigated.In the context of data conversion, by using two low-power analog buffers instead of the conventional binary weighted capacitive array, a low-power 8-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an area efficient digital-to-analog converter (DAC) architecture is proposed. Furthermore, time-mode ADC as an alternative area and power-efficient structure is discussed and a highly linear, wide-input-range voltage-to-time converter (VTC) is presented and experimentally evaluated.In the context of efficient power converters, through optimizing the bias voltage of the gate of switching transistors in a conventional differential rectifier, three high-efficiency RF rectifier architectures, namely, gate-boosted, auxiliary-cell biased, and quasi-floating-gate (QFG)-biased rectifiers areproposed. Furthermore, through dynamically adjusting the input capacitance, a dual-band matching approach for RF rectifiers is presented. The proposed QFG-biased rectifier is incorporated and analyzed in a wake-up radio front-end. Also, backscattering method as a power efficient scheme during the transmit mode is studied in the context of biomedical implants. Furthermore, based on the techniques developed for enhancing the efficiency of the rectifier, an ultra-low-power complementary metal-oxide-semiconductor ( CMOS ) voltage-controlled ring oscillator architecture is proposed.The proposed building blocks and systems, namely, ADC, rectifiers, wake-up radio structure, and voltage-controlled ring-oscillator architecture are designed in a 0.13-µm CMOS technology and their performances are verified through post-layout simulation and/or measurement results.

View record

On the design of high-voltage analog front-end circuits for capacitive micromachined ultrasonic transducers (CMUT) (2014)

In ultrasound imaging, capacitive micromachined ultrasonic transducer (CMUT) technology has become a promising alternative to conventional piezoelectric- based technology. This work focuses on various aspects of CMUT-based imaging technologies. In the context of CMUT design and integration with associated electronics, flexible and reliable CMUT models that can be seamlessly simulated with the read-out circuits and provide insights in the system-level performance are of great importance. This work proposes a generic Verilog-AMS model for CMUT sensors that takes into account the non-linearities, dynamic behavior and harmonic resonances of the CMUT. This model is able to provide reliable estimations of the pull-in voltage as well as the resonance frequency and the spring softening effect.To improve the signal-to-noise ratio (SNR), integrating the CMUT transducer with the front-end electronics is critical. Design and implementation of a comprehensive analog front-end system in a 0.8μm high-voltage CMOS technology which includes high-voltage and fast-switching transmitters as well as low-power variable-gain receivers is presented. Co-simulation of the front-end electronics and the CMUT model demonstrates full system functionality. Experimental results of the system at the transmit mode confirm the reliability of this co-simulation. An on-chip adaptive biasing unit (ABU) is also included in the design which aims to improve the CMUT receive sensitivity. The ABU consists of a DC-DC converter to generate a range of bias voltage levels and a digital control unit to select the desired voltage. Co- simulation of the ABU with the Verilog-AMS model confirms the increase in the CMUT sensitivity in receive mode.In the context of CMUT super-resolution imaging, we present the design of a transceiver circuit in a 0.35μm high-voltage CMOS technology that supports both the fundamental and asymmetric modes of operation. The transmitter provides high- voltage pulses to the CMUT electrodes. The receiver includes transimpedance analog adders to add the fundamental mode in-phase signals as well as differential amplifiers to combine the out-of-phase signals of the asymmetric modes. Furthermore, low- power variable-gain stages are included to amplify the resulting signals and facilitate interfacing to the ultrasound imaging machine for additional processing and display. The design functionality is confirmed by experimental results.

View record

Design techniques for high-speed low-power wireline receivers (2013)

High-speed data transmission through wireline links, either copper or optical based, has become the backbone for modern communication infrastructure. Since at multi-Gb/s data rates the transmitted signal is attenuated and distorted by the channel, sophisticated analog front-end and/or digital signal processing are required at the receiver (RX) to recover data and clock from the received signal.In this thesis, both analog- and digital-based receivers are investigated, and power-reduction techniques are exploited at both system- and circuit levels. A speculative successive-approximation register (speculative/SAR) digitization algorithm is proposed for use at the receiver front-end of digital receivers that combines equalization and data recovery with the digitization step at the front-end analog-to-digital converter (ADC). Furthermore, architecture for quadrature clock generation is proposed which is of use in both analog and digital receivers. Then, an analog clock and data recovery (CDR) architecture suitable for high data rates (e.g., beyond 10 Gb/s) is proposed that utilizes a wideband data phase generation technique to facilitate mixer-based phase detection. The CDR architecture is implemented and experimentally validated for a 12.5 Gb/s system. Finally, a mixed-mode hardware-efficient CDR architecture is proposed that exploits both analog and digital design techniques to reach a robust operation suited for long-haul optical link communications. Proof-of-concept prototypes of the proposed RX architectures are designed and implemented in 65 nm and 90 nm CMOS processes. The prototypes are successfully tested. Note that although individual performance merits of the each prototype may not necessarily outperform that of the state-of-the-art, however, the prototypes confirm the feasibility of the proposed structure. Furthermore, the proposed architectures can be used at higher data rates particularly if more advanced technologies with higher device transit frequency, (fT), is used.

View record

Design techniques for high-temperature analog and mixed-signal integrated circuits (2013)

Reliable high-temperature analog and mixed-signal CMOS circuits are required for several applications including aerospace, automotive control, oil field instrumentation, and pulp and paper digesters. In particular, in this work we focus on the design of key building blocks of a miniature sensor interface system that is intended to operate in a pulp and paper digester and collect and record sensory data such as pressureand temperature along its trajectory within the digester. The temperature inside thedigester can be as high as 180℃.Design considerations and techniques for implementing these building blocks both atcomponent- and circuit-levels are presented. At the component level, techniques fordesigning monolithic resistors with a desired temperature coefficient (TC) are proposed, and an analysis on the effects of design parameters such as resistor length, width and the number of fingers on the TC of such multi-finger resistor structures is presented. Furthermore, since the foundry-provided transistor models are typicallyvalid up to 125℃, various NMOS and PMOS transistors with diff erent sizes are implemented to study their behaviour at high temperature. Based on our observations, a suitable sizing for transistors is suggested for circuits operating up to 200℃. At the circuit-level, several key building blocks such as bias circuits, voltage references and oscillators are designed and proof-of-concept prototypes are implemented in astandard 0.13 ㎛ CMOS process. The operation of the circuits is experimentallyvalidated over the temperature range of interest, namely, 25 to 200℃.Also, a low-complexity resistive and capacitive temperature-compensation techniquesfor high-temperature relaxation oscillators is proposed. Although the temperaturestability of the proposed oscillator (108 ppm/℃) compares favourably with that ofstate-of-the-art designs, it occupies 0.007 mm² which is 2.3 to 114 times smaller thanother comparable designs. Also, the proposed circuit operates reliably up to 200℃(as compared to 125℃ in other designs).Although the proposed techniques are only validated using proof-of-concept prototypes in a 0.13 ㎛ CMOS technology, they are general and our preliminary studies onseveral technologies indicate that the techniques can be implemented in other CMOStechnologies as well.

View record

Modelling and application of spiral inductors in CMOS LC-VCOs (2013)

Communication systems are essential components of our everyday lives and they facilitate accessing and using the ever-increasing amounts of data that have surrounded us. The main objective of this research is to present solutions at the device, circuit, and system levels for key passive and active circuit building blocks of communication systems, namely, monolithic passive inductors and inductor-based voltage-controlled oscillators (LC-VCOs). These components are almost ubiquitously used in integrated wireless and wireline communication transceivers, as well as other computing devices. Key contributions of this work are as follows: In the context of monolithic inductors, we have studied different inductor structures such as doubly-stacked inductors, vertical inductors, and coupled-rings. We have developed circuit models to accurately estimate their inductance and quality factor. The proposed analytical expressions provide designers with a reasonable estimate of their circuit performance and layout constraints. The result of proposed analyses is verified by the measurement results of test structures implemented in CMOS technology.Regarding LC-VCOs, we have studied the effect of large signal oscillations on such VCOs by developing a mathematical model to solve the non-linear differential equation governing the LC tank circuit. The study shows that the VCO frequency and the amplitude of higher order harmonics are functions of circuit parameters such as the C-V characteristics of the varactor and the oscillation amplitude. Also, a low- power technique to boost the output amplitude of push-push VCOs is introduced. Measurement results of a proof-of-concept prototype test chip in 90-nm CMOS confirm the usefulness of the proposed technique.Finally, at the system level, we present an analytical model to study the effect of coupling between adjacent LC-VCOs closely integrated on the same chip. This is usually the case in high-speed wireline transceivers such as those used in serial links. The proposed model explains the behavior of spurious sidebands as observed in the frequency spectrum of closely-running adjacent links. A redundant frequency mapping scheme is proposed that significantly reduces this coupling effect. Measurement results of a highly packable clock synthesizer in a 65-nm CMOS confirm the validity of the analytical model and the effectiveness of the proposed mapping technique.

View record

On the use of body biasing to improve the performance of CMOS RF front-end building blocks (2013)

Body biasing is commonly used in digital and low-power analog integrated circuits to adjust the threshold voltage of complementary metal-oxide-semiconductor (CMOS) transistors and to lower the supply voltage. In this work, the application of body biasing to improve the performance of four of the main building blocks of CMOS radio-frequency (RF) front-ends is explored. Here, the body-biasing technique is used in conjunction with other design techniques and provides an extra degree of freedom in the design of CMOS RF front-end building blocks including low-noise amplifiers (LNAs), active down-conversion mixers, voltage-controlled oscillators (VCOs), and power amplifiers (PAs). The performance improvements are mainly related to noise and linearity of these building blocks and have been achieved through adjusting the values of the bulk-source transconductance, the source-bulk capacitance, and the threshold voltage of the MOS transistors. Body biasing is applied in multi-stage LNAs to improve their noise figure and linearity as well as to adjust the gain. Body biasing is used to improve the linearity of active down-conversion mixers with gradual LO switching by enhancing the linearity of the LO stage. Body biasing is used in cross-coupled LC VCOs to improve their phase noise performance by forward body biasing of core transistors which lowers the duty cycle in class-C mode of operation. In active-inductor-based LC VCOs, body biasing is used to increase the tuning range of active inductors and thus the oscillation frequency. Finally, body biasing is in the predistortion stage of class-AB PAs to improve the linearity by compensating for the voltage-dependent nonlinear gate-source capacitance of the input transistor of the PA. In all cases, these improvements are achieved with minimal overhead on circuit-level complexity and power consumption of the overall system. The proposed applications of body-biasing technique are validated through measurements on different proof-of-concept prototypes fabricated in 0.13-µm, 90-nm, and 65-nm CMOS technologies.

View record

A low-phase-noise mm-wave oscillator and its application in a low-power polar transmitter (2012)

Over the past decade, there have been substantial activities as well as changes in the design of high-speed radio-frequency millimeter-wave (mm-wave) integrated transceivers and their building blocks such as oscillators, mixers, low-noise amplifiers, and power amplifiers. One of the popular mm-wave frequency bands is the 7 GHz unlicensed band available around 60 GHz, which is attractive for a variety of applications including wireless local area networks(WLANs), short-range high data-rate wireless personal area networks (WPANs), and vehicular radar. One of the critical challenges in the design of 60 GHz integrated transceivers is the local oscillator signal generation. One of the main objectives of this thesis is to present and experimentally validate techniques to achieve better phase noise for high frequency oscillators, especially for high data rate applications.This thesis studies the phase noise performance of a new rotary-wave coupled oscillator. The presented oscillator is a traveling-wave oscillator with a reduced phase distortion. This oscillator hybridizes the standing-wave oscillator and travelling-wave oscillator to take advantage of the benefits of each structure, i.e., low phase noise and low power consumption. The structure of this circuit is based on a travelling-wave oscillator tapped with four standing-wave oscillators along a transmission line to accurately provide multiphase outputs. This oscillator produces eight phases, 45° apart from each other. A proof-of-concept prototype oscillator, fabricated in a 0.13-μm CMOS technology, provides a −17.5 dBm tone at 67 GHz and achieves a 5.2 GHz tuning range (8%) while it consumes 43.2 mW from a 1.2-V supply. The measured phase noise is −87 dBc/Hz (−102 dBc/Hz) at 1 MHz (10 MHz) offset. As an application for this type of oscillator, a circular quadrature-amplitude modulation (QAM) small-signal polar transmitter is proposed and a proof-of-concept 16-level QAM modulator is designed and simulated. In this architecture, the proposed oscillator has been combined with an 8-to-1 multiplexer and four-level variable-gain amplifier to implement the QAM transmitter. Based on the post-layout simulation results, (which are in an excellent agreement with measured results for the oscillator block) the transmitter consumes 25% less power as compared to state-of-the-art 60-GHz transmitters with comparable performance.

View record

Techniques for clock skew reduction over intra-die process, voltage, and temperature variations (2010)

Synchronous clock distribution continues to be the dominant timing methodology for very large scale integration circuit designs. As processes shrink, clock speeds increase, and die sizes grow, an increasingly larger percentage of the clock period is being lost to skew and jitter. New techniques to reduce clock skew and jitter must be deployed to utilize the faster clock frequencies possible with future process technologies, especially in the presence of on-chip process-voltage-temperature (PVT) variations. This dissertation first proposes a pre-silicon design modification to symmetric clock buffers of traditional clock distribution networks. Specifically, clock performance is improved by targeting the critical clock edge (the edge activating rising edge-triggered flip-flops) while relaxing the requirements of the non-critical edge. This system uses alternating, asymmetric clock buffers to focus inverter resources on only one edge of the clock pulse; hence, it is called Single Edge Clocking (SEC). A novel re-design of the traditional clock buffer is proposed as a drop-in replacement for existing clock distribution networks, yielding timing performance improvements of over 20% in latency and skew, and up to 30% in jitter; alternatively, these timing advantages could be traded off to reduce clock buffer area and power by 33% and 12%, respectively. PVT variations, especially intra-die, increasingly upset the distribution of a synchronized clock signal, even in properly balanced clock tree networks. Hence, active clock deskewing becomes necessary to tune out unwanted clock skew after chip fabrication. This dissertation proposes a post-silicon autonomous deskewing system using tunable buffers to dynamically reduce clock skew. The operation of a specially designed phase detector is described, and four such phase detectors are used to construct a stable, autonomously locking Quad Ring Tuning (QRT) configuration that effectively links together four distributed Delay-Locked Loops (DLLs) without the need for any system-level controller. This cyclic, unidirectional, self-controlled, quad-DLL ring tuning technique is then implemented hierarchically to dynamically adjust clock signal delays across an entire chip during normal circuit operation. A simple form of the two-level QRT system is presented for a generic H-tree distribution network, demonstrating stable locking behavior and more than 50% average reduction in full-chip clock skew.

View record

A frequency-translating hybrid architecture for wideband analog-to-digital converters (2009)

Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement.In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth.In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage.

View record

Master's Student Supervision (2010-2017)
Low-power temperature sensing system for biomedical applications (2018)

Implantable sensors have been used to improve monitoring and diagnosis of health-related parameters while allowing patients to lead a relatively normal life. Using data from such sensors, one can detect abnormal conditions at early stages and facilitate the prevention of potentially serious consequences. Recent technological advances in integrated circuits, wireless communications, and physiological sensing allow miniature, lightweight, ultra-low-power, intelligent monitoring devices. In this thesis, we focus on an electro-thermally active stent technology for management of in-stent restenosis (i.e., re-narrowing of artery at the stented site). Various studies reporting hyperthermia treatments of restenosis through stent heating have shown promising results, i.e., moderate local heating prevents restenosis by limiting cell proliferation. To remotely warm up the stent, we intend to harvest power from a dedicated source outside of the patient’s body and convert it to heat. However, if there is no control over temperature, the stent temperature may increase unboundedly, which would have adverse effects. The main objective of this thesis is to design a low-power, accurate temperature sensing system with a small footprint. Further, the required power to operate the temperature sensor should be harvested. In this work, two different temperature telemonitoring systems have been designed and laid out in a 65-nm CMOS technology. Both systems have been fabricated and successfully validated. The first telemonitoring system converts the sensed temperature directly to a frequency in an unlicensed band and transmits it to an external reader. The system operates from a supply voltage of 0.7 V and a power consumption of 100 µW. The measured sensitivity of the system is 1.1 MHz/°C within the frequency band of 902 to 928 MHz. This system is capable of detecting temperature change to as low as 1 °C. The sensor interface circuit of our second telemonitoring system converts the temperature to duty-cycle and sends sensory data out using an on-off-keying modulation system. The pulse width of the transmitted signal is proportional to e temperature. Measurement results of a proof-of-concept prototype show that the system operates from a supply voltage of as low as 0.6 V while consuming 115 µW.

View record

An investigation on the characteristics of conical coils for wireless power transfer systems (2017)

Historically, there have been many efforts to transfer power over the air medium and eliminate the necessity of conducting wires. Recent success stories on this direction has empowered unforeseen applications in many fields ranging from biomedical, wearable, food industry, and consumer products to electric vehicles. In this work, conical coil structure is presented as a viable solution to improve the efficiency of magnetically coupled wireless power transfer (WPT) systems. It is shown, both qualitatively and quantitatively, that the use of conical inductors in place of traditional planar coils increases the self-resonance frequency of transmitter resonator while maintaining the flux linkage to the receiver side. Electromagnetic (EM) and circuit simulations predict an efficiency increase using conical coils in wireless power transfer link. The measurement results of a prototype 3-coil structure built based on the conical structure confirm the validity of simulation results. The analysis, design, and characterization comparison of WPT systems that use both planar and conical coils is also presented. A power transfer efficiency of up to 53.9% is achieved for a 4-coil WPT system employing conical coil resonators that are 50 cm apart (which translates into the separation distance of ~1.5× the diameter of the resonators). In contrast, the same system using planar resonators achieves a power transfer efficiency of 32.8%. Thus, employing conical coils improves the power transfer efficiency by a factor of up to 1.6×. Finally, an adaptive control mechanism to improve the efficiency of magnetically-coupled resonators (MCRs) is presented. To minimize the degradation in power transfer efficiency, the proposed system dynamically adjusts the capacitance of MCRs as the distance between the transmitter (TX) and receiver (RX) coils changes. The control unit operates in a self-sufficient manner through rectifying a portion of the AC signal present on TX and RX coils. A proof-of-concept circuit operating at 13.56 MHz is designed in a 0.13 μm CMOS technology and the simulation results confirm the validity of the proposed scheme.

View record

On the design of low-voltage power-efficient CMOS active mixers (2013)

No abstract available.

A low-power 10-bit 50 MS/s CMOS successive approximation register ADC (2012)

An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to a few tens of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for data communication, imaging, and video systems. With the rapid growth in the number of portable devices, low-power design with higher performance is desired to increase the battery longevity as well as meeting the ever increasing performance requirement, which impose significant challenges to the ADC design. Successive approximation register (SAR) ADCs are one of the candidate structures for low power ADCs, and due to the advancements in the fabrication technologies they have been able to achieve medium sampling rates with a resolution of 10 bit. In this work, an ultra low-power 10-bit 50-MS/s SAR ADC is presented. To reduce the power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor digital-to-analog converter (DAC) that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is improved by modifying the capacitor bank so that the bridge capacitor is an integer multiple of the unit capacitor (as opposed to fractional multiple in the conventional circuits) and by including two dummy unit capacitors connected to ground. The proposed 10-bit ADC is designed and simulated using a 90-nm CMOS technology. Post-layout simulation results show that at 1.0-V supply and 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB and consumes 0.32 mW with an input capacitance of 0.48 pF, resulting in a figure of merit (FoM) of 8.44 fJ/conversion-step. A proof-of-concept prototype is fabricated in 90-nm CMOS technology and is tested. The ADC core occupies an active area of 215×215 μm². Due to an unexpected problem with the measurement setup, at-speed testing was not possible and the test was done at 1 MS/s. The ADC achieves an ENOB of 7.51 with a power consumption of 51 μW. The reasons for subpar performance of the prototype design and potential solutions to improve it are discussed in detail.

View record

A study of two wideband CMOS LC-VCO structures (2012)

Phase-locked loops (PLLs) are widely used in telecommunication, radio, and computer applications. This thesis focuses on the study of wide-band PLLs, as they are a critical building block of many wireless and wireline systems. In particular, wide tuning range, low phase noise, and low power are desirable attributes for multi-standard and multi-band communication systems. One of the most critical components in a PLL is the voltage-controlled oscillator (VCO). In this work, two techniques for implementing a wide-tuning-range LC-VCO are presented. As a proof of concept, the techniques are used to design and layout two 13-GHz LC-VCOs, which are fabricated in a 90-nm CMOS technology and successfully tested. One design (Design A) uses two VCO cores and has an extra source-follower buffer while the other (Design B) uses one VCO core with a bank of switched capacitors. The 90-nm CMOS prototypes operate from a supply of 1.2 V. The Design A prototype has a 28.20% tuning range and a phase noise of ‒90.98 dBc/Hz at 1 MHz offset from the carrier, while the Design B prototype has a 24.42% tuning range and a phase noise of ‒94.20 dBc/Hz at 1 MHz offset. This measured performance is comparable with state-of-the-art wide-tuning-range VCOs. The total chip size, excluding pads, is 0.335 × 0.750 mm² and 0.316 × 0.425 mm² for Designs A and B, respectively. It was found that the addition of the source-follower buffer allows the VCO to function at a higher frequency, while the presence of the switched capacitor tends to deteriorate phase noise.

View record

A programmable-gain amplifier and an active inductor for in-vehicle power line communications (2011)

In-vehicle power-line communication (VPLC) is a communication technique that usesthe power lines of the vehicle for data transmission. Based on the measurements of the powerline communication channel, the channel response is characterized as frequency selective,time and location dependent with high signal attenuation. Also, the access impedancechanges a lot in different frequency ranges. These properties impose design challenges atboth system level and circuit levels of a VPLC system. This thesis presents the design of twocritical building blocks of a VPLC system, namely, a variable gain amplifier (VGA) and anactive inductor.VGAs are used to amplify the signal to a predefined level without introducing too muchdistortion. The presented VGA design targets a 0.13μm CMOS technology. The VGA designis discussed in detail. Gm-boosting technique is used to both increases the linearity andprovide a programmable 0 dB to 60 dB gain over a broadband. Furthermore, the gain isstable over a wide range of temperatures. The circuit is fabricated and tested, and themeasured results are in good agreement with the simulation results.Inductors are commonly used in impedance matching networks. In this work, an activeinductor circuit is designed which provides a wide tuning range for VPLC LC matchingnetworks. Active inductor is a good candidate to replace the passive inductor in the LCmatching network since it has a smaller area, wider tuning range, and a higher quality-factor.The designed active inductor is a fully differential grounded Gyrator-C active inductor.Simulation results confirm that the inductor has wide tuning range with linear tuning ability;however, its bandwidth is limited.The circuit design for this VPLC system is challenging, the preliminary results of theproposed circuits show some promise; however, further work is still needed to improve theperformance.

View record

An efficient CMOS RF power extraction circuit for long-range passive RFID tags (2011)

Effective matching and efficient power conversion play key roles in long-range power telemetry. This thesis discusses challenges and suggests solutions for long-range power telemetry with an emphasis on radio-frequencyidentification (RFID) applications. As a proof-of-concept a radio-frequency(RF) power harvesting system in a 0.13-µm CMOS technology is designed,fabricated, and successfully tested.The RF power harvesting system must maintain matching over the thewide operation frequency range of passive RFID tags, mandated by EPC-global. In this work, we first analyze the series-inductor matching networkand show that there is a trade-o between bandwidth and efficiency. Wethen derive some guidelines for matching circuit design for RFID tags. To solve the matching problem over a wide frequency range, an adaptive matching system is proposed. At the startup, this system turns on while the restof the chip is still inactive, and automatically tunes the matching networkto achieve its maximum output voltage. Then the rest of the chip wakes up and functions as normal.A new CMOS rectifier stage is also proposed. This stage is capable ofefficient operation even with very low input powers. In addition, this rectifierstage can be cascaded to reach higher output voltages without significantly compromising the overall efficiency. Combination of low-power performance and cascadability makes this rectifier suitable for long-range RFID tags.The test setup and measurement results are also discussed in a separatechapter. The measurement results show a 50% rectifiers efficiency at 4-µWinput power. To the best of our knowledge, to date, this is the highestefficiency reported for rectifiers operating at such a low input power. Also,as compared to the output voltage at the nominal center frequency of theinput matching network, the system shows less than 6% drop in outputvoltage over the entire 55-MHz bandwidth of the system which verifies the effectiveness of adaptive matching.

View record

A dual-tuned active-inductor-based LC-VCO and its application in a wideband PLL (2010)

A wideband phase-locked loop (PLL) allows chip designers to use a single PLL for multiple communication standards. In wireline transceivers, such a wideband PLL can be incorporated as a part of a programmable (software-defined) de-serializer, or replace several PLLs for multiple standards if the bands are not used simultaneously. This thesis presents the design of a wideband PLL targeting wireline communication standards with clock frequencies between 0.5 and 5 GHz. To the author’s knowledge it is the first wideband PLL using an active-inductor-based VCO and its measured performance results compare favorably, especially in power and area, with state-of-the-art wideband PLLs. Further contributions include: the derivation of the lumped-element model of the PMOS-based two-stage active-inductor, noise contributions of the active-inductor VCO, and a compensated charge pump to reduce locked phase offsets. Design targets a 0.13-μm CMOS process. In simulations with extracted parasitics, the active-inductor VCO covers the desired 0.5 to 5 GHz range with a small margin. It exhibits coarse and fine VCO gains of 12.8 and 1.48 GHz/V, respectively, across the entire tuning range. The phase noise of the VCO is less than or equal to –78 dBc/Hz at a 1 MHz offset from the carrier. As compared to simulations, the measured maximum operating frequency of the VCO is reduced by 12 %, spanning frequencies up to 4.4 GHz. The measured phase noise degrades by approximately 10 dBc/Hz.The PLL uses a phase-frequency detector to lock to incoming signal across its entire frequency range and a linear compensated phase detector to achieve less than 5° phase offset between the incoming and locked clocks and a measured output jitter of 1.3 ps_rms for a VCO output frequency of 4 GHz. The PLL consumes between 34 mW and 48 mW.

View record

A hybrid phase-locked loop for clock and data recovery applications (2010)

Clock and data recovery (CDR) circuits are among critical building blocks of wireline receivers. In these receivers, typically after compensating for the adverse effects of thechannel by an equalizer, the received signal is processed to the CDR block. The timing of the signal is first extracted (clock recovery), and then the actual data is recovered (data recovery). To recover the clock, phase-locked loops (PLLs) are usually used. The PLL output can track the phase and the frequency of its input.In this thesis, a hybrid PLL architecture is proposed. The PLL starts its operation using a binary phase/frequency detector (PFD) to achieve a fast lock and a wide tuning range. The operation is then automatically switched to a linear phase detector (PD) to achieve a low jitter clock signal upon lock, and finally the bandwidth is decreased to decrease the output jitter even more. Automatic switching of the operation from the binary to the linear PD is achieved by detecting the point at which the clock frequency crosses the data frequency. This PLL structure is particularly suitable for CDR applications, as its output is insensitive to continuous data streams.Also, a feedback-based technique is used in the charge pump (CP) to increase its swing. This is done by detecting the change in the drain-source voltages of the current source transistors of the CP and changing their gate-source voltages in a closed-loop feedback system to keep their currents constant. The PLL is designed and simulated in a 0.13 μm CMOS technology. Post-layout simulations show that the tuning range of the PLL is from ∼8.3 GHz to 9.6 GHz, and it consumes about 35 mW from a 1.2 V supply and has a deterministic jitter of about 35 fs. The total random jitter of the designed PLL is about 0.1 unit interval (UI) (11.7 ps with a clock frequency of 8.5 GHz). The worst-case lock time of the PLL is slightly less than 30 ns.

View record

Design of efficient wireless power-transfer system and piezoelectric transducer for sonoporation-based drug delivery implants (2010)

Implantable devices are becoming popular in health and medical applications. In particular, localized and controlled drug release systems have gained clinical relevance in the treatment of many diseases. The power requirement for sonoporation-based systems is comparatively higher than that of other implantable devices. Efficient wireless power delivery and efficient small ultrasound transducer with low aspect ratio (G = length/thickness) is required to obtain high power transfer efficiency for implantable sonoporation based system.To provide power wirelessly to implantable device, resonance-based wireless power delivery system is considered. This system is modeled and optimized for given design constraints. The prototype 4-coil system achieves at least 2 × more efficiency as compared to prior art inductive links operating with comparable size and operating range. Withimplanted coil of diameter 22 mm and at operating distance of 20 mm, power transfer efficiency of 82% is achieved. The focus of the work is on power delivery in implantable devices. However, the method is general and can be applied to other applications that use wireless power transfer.Sono-Dynamic Therapy (SDT) uses ultrasonic cavitation to enhance the cytotoxicity of chemotherapeutic drugs. SDT requires ultrasound transducer to generate cavities. For implantable application, high electro-mechanical conversion efficiency of transducer is required to achieve high system efficiency and low heat losses in tissues. In the present work, identification of key parameters for transducer selection for implantable sonotherapy systems are given. Effects of ultrasound transducer’s aspect ratio reduction is analyzed and reduction in electro-acoustic conversion efficiency is explained using mode coupling between resonance modes of transducer. Energy harvesting and driver circuit is presentedto convert wirelessly received power to drive transducer to generate acoustic waves.This work demonstrates the first prototype of a wirelessly powered sonoporation-basedimplantable system. Though only two blocks of the prototype are optimized, overall systemefficiency is measured as 2.04 % which is close to the theoretical value of 2.24 % of presentdesign. By using an efficient power amplifier (class-E amplifier, efficiency 80%), an overallsystem efficiency of 22% can be achieved.

View record

Recent Tri-Agency Grants

The following is a selection of grants for which the faculty member was principal investigator or co-investigator. Currently, the list only covers Canadian Tri-Agency grants from years 2013/14-2016/17 and excludes grants from any other agencies.

  • Test Infrastructure for Next-Generation (5G) Wireless Communication and Internet of Things - Natural Sciences and Engineering Research Council of Canada (NSERC) - Research Tools and Instruments (2016/2017)
  • Power and data transfer over coaxial cable for robotic sensory data collection - Natural Sciences and Engineering Research Council of Canada (NSERC) - Engage Grants Program (2016/2017)
  • Realizing and testing of a low-power 3-D gesture tracking circuit for IoT and wearable computing applications - Natural Sciences and Engineering Research Council of Canada (NSERC) - Engage Grants Program (2015/2016)
  • 3D Thin-Film Coating for Micro/Nanodevice Study and Prototyping - Natural Sciences and Engineering Research Council of Canada (NSERC) - Research Tools and Instruments - Category 1 (2015/2016)
  • High-voltage electrochemical impedance spectroscopy - Natural Sciences and Engineering Research Council of Canada (NSERC) - Engage Grants Program (2015/2016)
  • Integration of INTERCONNECT and Cadence with an emphasis on co-simulation of CMOS drivers and optical ring modulators - Industrial Research and Development Internship (IRDI) Program - Networks of Centres of Excellence (NCE) - (2015/2016)
  • Design and development of a high-resolution sensory system for detection of biogenic signals - Natural Sciences and Engineering Research Council of Canada (NSERC) - Engage Plus Grants (2015/2016)
  • Remote wireless charging and energy harvesting - Mathematics of Information Technology and Complex Systems (MITACS) - Networks of Centres of Excellence (NCE) - Internship Funds (2014/2015)
  • Design and development of a high-resolution sensory system for detection of biogenic signals - Natural Sciences and Engineering Research Council of Canada (NSERC) - Engage Grants Program (2014/2015)
  • Crosstalk-reduced large scale silicon photonic integrated circuit switch array - Natural Sciences and Engineering Research Council of Canada (NSERC) - Collaborative Research and Development Grants - Project (2014/2015)
  • Active stent based endohyperthermia system for inhibition of in-stent restenosis - Natural Sciences and Engineering Research Council of Canada (NSERC) - Collaborative Health Research Projects (2014/2015)
  • Infrastructure for assembly and test of microsystems for communication, silicon-photonics, biomedical, and sensory applications - Natural Sciences and Engineering Research Council of Canada (NSERC) - Research Tools and Instruments - Category 1 (2013/2014)
  • Design, verification, and test of analog and mised-signal integrated circuits with an emphasis on PLLs - Natural Sciences and Engineering Research Council of Canada (NSERC) - Collaborative Research and Development Grants - Project (2013/2014)
  • Design and test of high-speed CMOS drivers for integrated silicon-photonics multi-wavelength transceivers - Natural Sciences and Engineering Research Council of Canada (NSERC) - Engage Grants Program (2013/2014)
  • People and planet friendly home - Natural Sciences and Engineering Research Council of Canada (NSERC) - Collaborative Research and Development Grants - Project (2013/2014)
  • Single-Chip 60-GHz wireless-photonic integrated circuit - Natural Sciences and Engineering Research Council of Canada (NSERC) - Strategic Projects (2013/2014)
  • Architectures and circuits or efficient highly integrated communication systems and microsystems - Natural Sciences and Engineering Research Council of Canada (NSERC) - Discovery Grants Program - Individual (2013/2014)
  • Silicon electronic-photonic integrated circuits (Si-EPIC) - Natural Sciences and Engineering Research Council of Canada (NSERC) - Collaborative Research and Training Experience (CREATE) Program (2013/2014)
  • Power line communications for electric vehicles - doing more with less wiring - The Automobile of the 21st Century (AUTO21) - Networks of Centres of Excellence (NCE) - Research (2013/2014)

Current Students & Alumni

This is a small sample of students and/or alumni that have been supervised by this researcher. It is not meant as a comprehensive list.
 
 

If this is your researcher profile you can log in to the Faculty & Staff portal to update your details and provide recruitment preferences.