Sudip Shekhar

Associate Professor

Relevant Degree Programs

 
 

Graduate Student Supervision

Doctoral Student Supervision (Jan 2008 - Nov 2020)
High-speed optoelectronic links for datacenters (2020)

Optoelectronic (O/E) links are necessary for inter/intra-datacenter communication. Driven by the need to support higher data throughput, breakthroughs in Silicon-photonics and innovative circuit techniques are needed to enable efficient, compact, and low-cost links across a wide range of interconnect lengths.For short-reach applications, where energy efficiency is a major concern, microring resonator (MRR)-based transmitters (TXs) promise low cost and dense multiplexing to replace their vertical-cavity surface-emitting laser (VCSEL)-based counterparts. This thesis presents an analysis of MRR-based links from the perspective of optical devices, circuits, and link budget and compares them to VCSEL-based links.On the receiver (RX) side, sensitivity enhancement is necessary to improve the link’s energy efficiency. Due to their multiplication gain, avalanche photodetectors (APDs) improve RX sensitivity. When implemented monolithically with the RX, they reduce cost and parasitics. An RX with noise-canceling active balun is presented. The RX works as part of the APD bias stabilization loop. The integrated O/E-RX achieves a measured sensitivity of -18.8dBm at 0.57pJ/b.A high-sensitivity, high-speed, and low-power RX demands solutions to the gain-bandwidth-power trade-offs. Accordingly, a current-mode receiver that eliminates the noisy and power-hungry front-end is proposed. The proposed design converts the single-ended PD current into differential currents and resolves the data using a current-based sense amplifier.For long-reach applications, where spectral efficiency is critical, coherent O/E links rely on advanced modulation and dual-polarization, leading to stringent link requirements. The TX requires high bandwidth (BW), linearity, swing, and reliability, while the RX requires minimizing noise and total harmonic distortion (THD) across gains and frequency.A linear high-swing driver for Mach-Zehnder modulator is presented. The driver uses a voltage breakdown enhancement technique to ensure reliability, and resistor-based capacitor-splitting technique to enhance BW. It achieves 6Vppd, 3.6% THD, and >40GHz BW, enabling >0.5Tb/s/wavelength operation.An auto-reconfigurable transimpedance amplifier satisfying the stringent noise-linearity conditions is presented. Operating on a single sense-voltage, it reduces base resistor noise, gain peaking, phase margin and fT degradation. Techniques such as collaborative offset and DC current cancellation are also described. The RX achieves a gain of 75.5dBOhm and an input-referred noise of 18.5pA/sqrt(Hz) at 42GHz BW, enabling >0.5Tb/s/wavelength operation.

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Reconfigurable silicon photonic integrated circuits (2020)

No abstract available.

Enabling practical deployment of silicon ring resonator-based systems (2018)

Microring resonators (MRRs) on silicon photonic platforms allow for low-power, dense, and large-scale manipulation of optical signals on-chip. MRR-based modulators, switches, and filters have become key building blocks in integrated optical circuits for applications in future data communications, high-performance computing, and sensing. This thesis presents solutions for overcoming several challenges towards practical deployment of MRR systems. The performance of MRR is highly susceptible to temperature and fabrication variations, which cause significant shifts in the MRR's spectral responses. In-resonator photoconductive heaters (IRPHs), formed by doping MRRs’ waveguides show high responsivities. As IRPHs do not require additional material depositions, photodetectors, or power taps and use the same contact pads for both sense and tune operations, they can be used to automatically tune and temperature stabilize MRRs without compromising the cost or area of the devices. Automatic tuning and stabilization of one- and two-ring filters are demonstrated.Multi-ring filters offer attractive spectral features such as wide pass-bands, steep roll-offs, and large extinction ratios. Using IRPHS, automatic tuning of a four-ring Vernier ring filter across a record 37.6 nm wavelength and wavelength locking to account for a record 65 degrees temperature variation is demonstrated. A tuning algorithm in which the number of iterations scales linearly with the number of coupled rings in the system is presented. As this method typically does not rely on the output spectral shape of the filter, it is applicable to a wider range of coupled resonator systems. Application of this tuning method is then demonstrated for various multi-ring filters by both simulation and experiment. Crosstalk can be a major source of signal degradation in large-scale MRR systems. Interchannel and intrachannel crosstalk of one- and two-ring MRR filters are experimentally investigated. The power penalties due to interchannel crosstalk are presented as functions of channel spacing and adjacent channel isolation. Intrachannel crosstalk of one-ring, cascaded, and series-coupled add-drop filters are compared and spectral conditions that will ensure low intrachannel crosstalk is presented. MRR filters with extremely small radii of 2.75 um, large free spectral ranges of 34.3 nm, and high thermal tuning efficiencies of 2.78 nm/mW are presented.

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Radio frequency CMOS: from ultra-high speed to ultra-low power (2018)

Over the last three decades, radio-frequency(RF) Complementary Metal-Oxide-Semiconductor(CMOS) electronics has made a huge impact in our world. Wireless Local Area Networks(WLANs), cellular networks, Global Positioning Systems(GPSs), and Bluetooth are a few examples where the impact of RF CMOS has led to rapid adoption and standardization of the technology. However, there still exists several challenging areas at the intersection of RF and CMOS where new paradigms must be established. This thesis summarizes the research to meet those goals as briefly described here: Research during the past decades provided CMOS solutions to RF applications that utilize the frequency spectrum up to 6 GHz. However, efficient system integration of mm-wave and THz in CMOS is still a challenging task. The THz spectrum is gaining interest due to its wider and less populated available spectrum, as well as its intriguing applications in molecular spectroscopy, imaging, and sensing. This band, although very useful, has been difficult to realize in hardware because of the limitations in CMOS electronics. In the first four chapters of this thesis, we investigate the challenge of implementing signal-sources at mm-wave and sub-THz frequencies using low-cost and versatile CMOS circuits, replacing the existing expensive solutions.Demand for embedded low-power electronics for wireless connectivity is growing due to the rapid proliferation of Internet-of-Things (IoT). Although Wireless Sensor Network(WSN) had been around for decades, some applications such as biomedical monitoring systems require ultra-low-power(ULP) and cost-effective wireless solutions. Research on energy-harvesting systems (e.g., RF energy harvesting, thermoelectric, etc.) and integrated-circuits(IC) bears the promise of medium-reach battery-free wireless connectivity solutions. In Chapters 5 and 6 of this thesis, multiple ULP wireless connectivity solutions for both commercial standards such as Bluetooth Low Energy(BLE) and custom-designed application-specific-radios are proposed and implemented in 40nm and 130nm CMOS technologies, respectively.Finally, application of RF electronics in power-electronics is studied in the last chapter. Although power-management integrated circuit is a well-developed field of research, PMICs still have existing bottlenecks (e.g., die area and output ripple) which can be addressed with the knowledge of RF electronics. In this thesis, feasibility of GHz-range converters is studied.

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Master's Student Supervision (2010 - 2018)
A differential push-pull voltage mode driver for vertical-cavity surface emitting laser (2018)

The unabated demand for data communication has led to a rapid growth in warehouse-sized datacenters where high-end servers transfer terabytes of data per second between the racks using optical data links. Vertical cavity surface-emitting laser (VCSEL) based optical links are widely popular in such datacenters for short-reach (
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Automatic tuning circuits for Mach-Zehnder interferometer optical switches (2018)

Optical communication networks are the foreseeable solution to meet the increasing demand for high data rates. An important part of a communication network is the network switch that facilitates the routing of data from sources to destinations, from a set of input streams to a set of output streams.Silicon photonics is poised to play a significant role in optical communication networks due to its suitability to build scalable and highly integrated photonic structures and systems, in addition to the use of established fabrication methods inherited from the electronics industry. One of the applications where silicon photonics can play a critical role is in implementing network switches. A Mach-Zehnder interferometer (MZI) is an optical device that is ideally suited to build network switches, as it can be dynamically controlled to achieve high-quality switching of optical signals. However, the performance of silicon photonics devices is sensitive to fluctuations in ambient temperature, fabrication tolerances, and device aging, and MZI devices are no exception. This work describes the factors that degrade the performance of an MZI switch, and then presents an electronic feedback system that monitors and automatically tunes a 1x2 MZI switch to its optimum operating point and compensate for the aforementioned performance-degrading factors. A design for a 2x2 MZI switch monitoring technique is also presented that uses feedforward interferometry to enable more efficient use of the MZI as a switch for two simultaneous optical inputs at different wavelengths, and an electronic feedback and tuning system for such switches is also demonstrated.

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Design and analysis of supply-noise-insensitive all-digital phase-locked loops (2018)

Phase-locked loops (PLLs) are widely used in communication and digital systems to generate high frequency clocks by multiplying a low-frequency reference clock. Scaling of complementary metal-oxide-semiconductor (CMOS) technology over the last decade has benefitted digital circuits by shrinking their size and reducing their power consumption. On the other hand, it has posed challenges for analog design because of the decreasing power supply voltage and output impedance of transistors. Therefore, an all-digital PLL (ADPLL) becomes increasingly preferable over its conventional analog counterparts in terms of area and design flexibility. PLLs employ an oscillator locked to the phase and frequency of the reference clock. An LC oscillator utilizes an inductor (L) to filter noise, but on-chip inductors require large area and need specific thick metal layers for low loss. Compared to LC oscillators, ring oscillators are more suitable for ADPLL implementation since they occupy smaller area and are compatible to digital CMOS processes without a thick-metal layer option. However, the oscillation frequency of a ring oscillator is determined by the propagation delay of the delay-cells, and thereby very susceptible to power supply noise. In fully-integrated systems, switching of large-scale digital circuits can create large supply ripples and degrade the noise performance of the PLL output. Low dropout (LDO) regulators as well as some cancellation techniques have been adopted in prior-art to mitigate the supply sensitivity of ring-oscillator based ADPLLs. However, these techniques suffer from supply voltage headroom, noise penalty, and design complexity. In this thesis, a low-complexity supply-noise-insensitive ADPLL is proposed that does not degrade the supply voltage headroom, and operates over a wide range of supply-noise amplitude. Fabricated in a 65nm CMOS process, the ADPLL achieves ~ 45 mV of tunable supply-noise-insensitive range where the frequency pushing is less than 10%, operating at 850 mV supply. With the tuning range from 1 GHz to 1.4 GHz, the ADPLL achieves 16 ps integrated jitter at 1.25 GHz output frequency and consumes 2.73 mW of power. 

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Transformer-enhanced high-performance voltage-controlled oscillators (2018)

We show that, in comparison to an inductor, an asymmetric transformercan improve the quality factor (Q) of an inductor-capacitor (LC) tank whenthe tank loss is dominated by the varactor. Near, and at mm-wave frequencies,varactors in complementary metal-oxide-semiconductor (CMOS)processes have significantly lower Q than inductors and transformers. Directlyconnecting a varactor to the core of an LC oscillator lowers tank Q,and the increased ratio of parasitic capacitance to total tank capacitancelimits frequency tuning range (FTR). Instead, magnetically coupling a varactorto the oscillator core using an asymmetric transformer, where the coreis connected to the primary and varactor to the secondary, increases tankQ. Furthermore, it permits doubling the varactor bias range and reducingthe parasitic capacitance seen at the varactor. Thus, both FTR andPhase Noise (PN) are improved simultaneously. Measurement results fortwo prototypes in 65nm CMOS are presented. A 25 GHz Voltage-controlledOscillator (VCO) shows an FTR of 29.8%, a PN of -106.6 dBc/Hz at 1 MHzoffset, and an FTR-inclusive Figure of Merit (FoMT ) of -195.04 dBc/Hz. A60 GHz self-mixing VCO, where the VCO core at 20 GHz is mixed with itscommon-mode 40 GHz tone, shows an FTR of 18.5%, a PN of -98.9 dBc/Hzat 1 MHz offset, and an FoMT of -193.4 dBc/Hz.

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A broadband self-interference cancellation circuit for simultaneous full-duplex radio applications (2017)

All wireless communication systems so far have employed either time division duplexing (TDD), where the transmitter and receiver share the same frequency band but operate in orthogonal time slots, or frequency division duplexing (FDD), where the time slots are shared but orthogonal frequency bands are used.In order to meet the requirements for the upcoming 5G mobile standards, the concept of simultaneous full-duplex is being actively pursued, where both time slots and frequency bands can be shared between the transmitter and the receiver. The greatest hurdle in achieving full-duplex communication is the self-interference from the transmitter that is several orders of magnitude stronger than the desired signal at the receiver. Realizing such broadband cancellation has been hitherto very challenging, because not only does it demand broadband cancellation in amplitude, phase and group delay of the echo signals, but also require such a cancellation circuit to be linear, low-noise and ultra-compact for a mobile form factor. This work will demonstrate the first self-interference radio-frequency cancellation circuit that achieves an 80 MHz linear time evolution (LTE) cancellation bandwidth in a linear, tunable, compact, and fully monolithic integrated circuit (IC) implementation for such full-duplex radios. A proof-of-concept prototype is realized in 0.13 µm complementary metal oxide semiconductor (CMOS) process that utilizes techniques such as frequency translations and baseband Hilbert transforms to attain a measured 23 dB of self-interference cancellation over an 80MHz signal bandwidth. The entire circuit consumes 34 mW from a 1.2V supply in an active area of just 0.84 mm².

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