Guangrui Xia

Associate Professor

Relevant Thesis-Based Degree Programs


Graduate Student Supervision

Doctoral Student Supervision

Dissertations completed in 2010 or later are listed below. Please note that there is a 6-12 month delay to add the latest dissertations.

Monolithic integration of 850 nm and 940 nm vertical cavity surface emitting lasers on bulk Si and Ge substrates (2024)

The production of vertical-cavity surface-emitting lasers (VCSELs), which are widely used in short-reach optical communication and three-dimensional (3D) sensing for consumer and industry products, currently heavily relies on 4-inch and 6-inch bulk GaAs wafers. This GaAs-based production limits production volume and increases manufacturing costs. To address these challenges, the monolithic integration of VCSELs on alternative substrates, which can be made beyond 6-inch size, to enable large-scale production on larger wafer sizes, thus higher throughput and lower cost, was investigated. Three technical pathways to replace conventional GaAs substrates were proposed. Two were to replace the GaAs substrates with engineered Si substrates using aspect ratio trapping (ART)-Ge transition layers and graded GaAsP buffer layers. The third one is to apply Ge wafers as the substrates for VCSEL epitaxy. In this study, these three approaches were thoroughly analyzed and evaluated based on material characterization and optical spectra measurement. The distributed Bragg reflectors (DBRs), the first and one major structural part of VCSELs, and full VCSELs were epitaxially grown on ART-Ge/Si substrates. DBRs were grown on GaAsP/Si substrates. For Ge substrates, DBRs and half-VCSELs growth were conducted. Bulk GaAs wafers were used as control samples for comparison. The material quality of growth on ART-Ge/Si substrates is low. The surface exhibits a high density of bumps and cracks, and the thickness of DBR layers is not uniform. Multiple techniques were tried for improvement, but the effects were limited. Due to supply chain difficulty, this approach was abandoned. In contrast, the GaAsP/Si-based DBRs demonstrate better material quality, but a crosshatch pattern leads to disappointing optical performance. After evaluation, the possibility of successful integration on Si substrates is low with limited resources available to the research. On the other hand, the Ge-based DBRs and half-VCSELs exhibit the best material and optical quality, comparable to those of the conventional GaAs-based counterparts. The monolithic integration on Ge substrates was successful, and it is the first study to show successful DBR and half VCSEL results on engineered Ge substrates with structure and fabrication details. Industry companies can use this study much more readily to adopt this technology.

View record

Enhanced performance of p-GaN gate AlGaN/GaN high-electron-mobility transistors for power applications (2021)

Gallium nitride (GaN) possesses excellent physical properties, such as a high critical electric field, a high saturation velocity, a high electron mobility, and a good thermal stability. Due to these superior material properties, GaN-based high-electron-mobility transistors (HEMTs) have performances superior to their silicon (Si) counterparts. They can operate at higher voltages, currents, frequencies, and temperatures, making them ideal devices for the next-generation high-efficiency power converters applications, such as phone chargers, electric vehicles, data centers and renewable energy. For switching applications, normally-off transistors are required to provide adequate safety. Due to the positive and stable threshold voltage, p-GaN gate HEMT technology is the most promising candidate among many options of normally-off HEMTs. Meanwhile, there are still some problems to be addressed (e.g., low threshold voltage, low gate breakdown voltage, gate reliability) for the p-GaN gate technology.In this dissertation, we present a comprehensive study of p-GaN gate HEMTs, including the work on failure mechanisms and three different methods to enhance the device performance. Chapter 1 includes a background review for power devices, GaN material properties and basic AlGaN/GaN HEMT structures. In Chapter 2, a typical fabrication process and test methods for p-GaN gate HEMTs are described in detail. Chapter 3 demonstrates a novel measurement and analysis method to identify three different gate failure mechanisms. Based on the baseline process in Chapter 2 and the analysis method in Chapter 3, three different structures aimed at enhancing the p-GaN gate HEMTs’ electrical performance and reliability are demonstrated in Chapters 3 to 6, including metal/graphene gates, ultra-high-resistance Au/Ti/p-GaN junctions, and doping engineering. The three different methods have their unique strengths. Chapter 7 concludes this work and suggests some future directions.

View record

Base Doping Profile Control for SiGe PNP HBTs (2016)

The aim of this thesis is to investigate three aspects related to phosphorus diffusion for doping profile control in PNP SiGe HBTs:We systematically and quantitatively investigated the impact of carbon and Ge on P diffusion in strained SiGe:C up to 18% Ge and 0.32% C through experiments, which shows that the incorporation of carbon to retard P diffusion is not as effective in SiGe as it is in Si. Models were established to calculate the effective P diffusivities as a function of carbon concentration. These models can also be applied to boron, phosphorus, arsenic and antimony diffusion in Si with the presence of carbon. These results indicate that the microscopic mechanism of P diffusion in Si₀.₈₂Ge₀.₁₈ has a small but non-negligible vacancy-mediated term. An experimental study of thermal nitridation effects on phosphorus diffusion in strained Si1-xGex and strained Si1-xGex:Cy was performed. P diffusivities under thermal nitridation (vacancy injection) and the effective inert condition were compared. The result shows that thermal nitridation can retard P diffusion in SiGe with up to 18% Ge content, but the effectiveness of this retardation decreases with increasing Ge and C content. The Ge dependence can be explained by the increasing contribution from vacancy-assisted mechanism for P diffusion in strained SiGe with the increasing Ge content. P tends to segregate out of SiGe region, which happens simultaneously with diffusion. A coupled diffusion and segregation model is needed to predict the P profile evolution at thin SiGe layers. The model was re-derived theoretically, where the contributions from diffusion and segregation to dopant flux are explicitly shown. The model is generic to coupled diffusion and segregation in inhomogeneous alloys, and provides a new approach in segregation coefficient extraction. This model is especially helpful for heterostructures with lattice mismatch strains. Experiments of coupled P diffusion and segregation were performed with graded SiGe layers for Ge molar fractions up to 0.18, which are relevant to PNP SiGe HBTs. The model was shown to describe both diffusion and segregation behavior well.

View record

A Systematic Study of Silicon Germanium Interdiffusion for Next Generation Semiconductor Devices (2014)

SiGe heterostructures with higher Ge fractions and larger Ge modulations, and thus higher compressive stress, are key structures for next-generation electronic and optoelectronic devices. Si-Ge interdiffusion during high temperature growth or fabrication steps changes the distribution of Ge fraction and stress, and increases atomic intermixing, which degrades device performance. It is of technological importance to study Si-Ge interdiffusion behaviours and build accurate Si-Ge interdiffusivity models.In this work, three aspects of Si-Ge interdiffusion behaviours were investigated both by experiments and by theoretical analysis.1) Based on the correlation between self-diffusivity, intrinsic diffusivity and interdiffusivity in binary alloy systems, a unified interdiffusivity model was built over the full Ge fraction range. It provides a zero-strain, no-dopant-effect, and low-dislocation-density reference for studies of more impacting factors. This model was then validated with literature data and our experimental data using different annealing techniques.Next, with the well-established reference, the impact of biaxial compressive strain on Si-Ge interdiffusion was further investigated under two specific strain scenarios: with full coherent strain and with partial strain. 2) Complete theoretical analysis was presented to address the compressive strain’s role in Si-Ge interdiffusion. The role of compressive strain was modeled in two aspects: a) strain energy contributes to the interdiffusion driving force; b) the strain derivative q' of interdiffusivity, reflecting the strain-induced changes of both prefactor and activation energy. For the temperature range (720 °C to 880 °C) and Ge fraction range (0.36 to 0.75), a temperature dependence of the strain derivative q', q'=-0.081T+110 eV/unit strain, was reported in Si-Ge interdiffusion. 3) For the case with partial strain, the apparent interdiffusivity model developed for the case with full coherent strain in 2) was modified to reflect strain change, and it was then validated with experimental data.In summary, a set of interdiffusivity models were established based on experimental data and theoretical analysis for three strain scenarios. These models can be employed to predict the thermal stability of SiGe heterostructures, and optimize the design of SiGe structures and of thermal budgets for next-generation SiGe based devices.

View record

Master's Student Supervision

Theses completed in 2010 or later are listed below. Please note that there is a 6-12 month delay to add the latest theses.

Design, prototyping, and optimization of a double pulse testing platform for high voltage dynamic testing of e-mode GaN HEMTs (2022)

Enhancement mode (E-mode) Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) have attracted much interest as a promising candidate for high-voltage energy-efficient power electronics in energy management and power conversion. They are used widely in solar energy grids, mobile base stations, satellite communication systems, electric vehicles, and consumer electronics. However, the switching and breakdown behaviors of E-mode GaN HEMTs under high voltage (> 200 V) conditions have not been fully investigated. As the gate driving design and the parasitic influence on the dynamic performance of E-mode GaN HEMTs are very different from those of conventional Si- and SiC-based power transistors, commonly used test benches do not work well. Therefore, component selection/design, measurement setup and board layouts need to be carefully re-considered for E-mode GaN HEMTs. In addition, the influence of parasitic parameters on the dynamic performance, which may lead to early breakdown problem, are not well studied. In this work, we aimed to address the above problems. We first designed, prototyped and optimized a double pulse testing (DPT) circuit and a DPT test platform to accurately capture the switching behavior of GaN E-mode HEMTs up to 600 V at a test current of 5 A. Using this DPT platform, we characterized the dynamic performance of some E-mode HEMTs in R&D and debugged the early breakdown problem. The results suggested that the early breakdown problem was mainly due to the parasitic elements introduced by the non-optimized circuit design and measurement setup.

View record

Monolithically integrated 940 nm AlxGa1-xAs distributed Bragg reflectors on bulk Si and Ge substrates (2022)

To address the dramatically increased market demand for vertical-cavity surface-emitting lasers (VCSELs) as light sources in distance and three-dimensional (3D) sensing for consumer and industry products, monolithic integration of VCSELs on bulk Si and Ge substrates was investigated in this work. It has the benefits of much larger wafer size and thus higher throughput, lower manufacturing cost, and the compatibility to integrate with silicon complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Distributed Bragg reflectors (DBRs), the first and fundamental part of VCSELs, were grown on three engineered bulk Si and Ge substrates: GaInAs/Ge substrate, graded-GaAsP/Si substrate, and aspect ratio trapping (ART)-Ge/Si substrate. A conventional bulk GaAs wafer was used as the control sample. Material characterization and optical performance measurement were performed on the fabricated DBRs.The GaInAs/Ge DBRs have comparable surface conditions and optical performance to the conventional bulk GaAs DBRs in terms of surface topology, thickness uniformity, and reflectance spectrum, qualifying GaInAs/Ge substrates for full VCSEL fabrication. The GaAsP/Si DBRs have defected surfaces with a relatively high density of surface bumps and a cross-hatch pattern. Moreover, the GaAsP/Si DBRs have irregular double-peak-shaped reflectance stopbands. The ART-Ge/Si DBRs have the worst surface quality, making them unsuitable for further VCSEL development. A surface scratch test was proposed and conducted to study the impact of the surface cross-hatch pattern on the DBR reflectance spectrum. A similar double-peak-shaped stopband was reproduced by manually introducing cross scratches on the high-quality bulk GaAs DBR surface. It strongly suggests that the cross-hatch pattern on the GaAsP/Si DBR surface is the root cause of the irregular double-peak-shaped stopband. A surface chemical mechanical polishing (CMP) was introduced as a potential solution to flatten the cross-hatch pattern and improve the reflectance spectrum. Data suggests the improvement of the double-peak-shaped stopband by reducing the surface roughness. However, the CMP process was with high variation and introduced new random scratches that affect the overall reflectance. Further epitaxy development and surface improvement are suggested to improve the bulk Si-based DBR performance.

View record

Novel few-layer black phosphorus nanostructure fabrication methods and DFT simulations (2020)

This paper reports the successful fabrication of large size few-layer blackphosphorus, and nano-patterning of 2-dimensional black phosphorus by a top-downlithography and etching approach. The wet etching process can etch selected regionsof few-layer black phosphorous with an atomic layer accuracy. This etch method isdeep-UV and e-beam lithography process compatible, and is free of oxygen andother common doping sources. 10 nm deep BP trenches were successfullyfabricated. Density function theory (DFT) simulations proved that that the etchingis bond-breaking-driven instead of intercalation-driven. It provides a feasiblepatterning approach for large-scale manufacturing of few-layer BP materials anddevices.The wet etching method was applied to fabricate twisted-stacked BP with theinterface as a Moiré pattern. DFT was used to simulate the phonon vibrations andRaman spectra of the Moiré pattern. Our DFT results indicate that a novel interlayerinteraction may exist in this kind of structures. Experimental work by Tao Fangconfirmed the simulation results.

View record

Impact of doping on epitaxial Ge thin film quality and Si-Ge interdiffusion (2018)

Germanium-on-silicon (Ge-on-Si) structure-based semiconductor devices are playing an increasingly important role in large-scale dense photonic integration, especially in silicon (Si) photonics. Si photonics has emerged as an effective solution to overcome the wiring limit imposed on integrated circuits with continued scaling by using optical interconnects instead metal interconnects. A Si-compatible laser is the last missing piece in optical interconnects on Si platforms. Recently, III-V lasers on Ge/Si substrates and Ge-on-Si lasers were demonstrated as the most promising candidates, in which Ge layers function as either the transition layers or the optical gain layers.For different applications, the requirements on Ge film quality and Ge/Si interface interdiffusion are different. Si-Ge interdiffusion during high-temperature growth or fabrication steps changes the distribution of Ge and increases atomic intermixing, which degrades device performance. However, studies on the doping impact on Ge film quality and Si-Ge interdiffusion are very limited, which were addressed in this work.We investigate Ge-on-Si film quality systematically under different types of doping conditions (phosphorus, arsenic and boron) for the first time. It’s found that the boron doping significantly impairs the Ge film quality, while arsenic and phosphorus can effectively reduce the threading dislocation density without the commonly used defect annealing. This provides a new method to fabricate high-quality Ge-on-Si films, which can avoid undesired Si-Ge interdiffusion.Si-Ge interdiffusion with different doping at Ge/Si interfaces has been investigated experimentally and theoretically. The enhancement of interdiffusion was observed in n-type (phosphorus and arsenic) doped Ge-on-Si. The phenomenon is attributed to the Fermi-level effect. A quantitative model of Si-Ge interdiffusion under high n-type doping was proposed. The model agrees well with the experimental data. This is also the first study on the quantitative modeling of Si-Ge interdiffusion with high n-type doping across the full Ge range.This work is of technical significance for the structure, doping and process design of Ge-on-Si structure-based devices including the two laser types mentioned above, Ge modulators and Ge photodetectors.

View record

Controllable and scalable thermal sublimation thinning of black phosphorus (2017)

Two-dimensional lamellar black phosphorus (BP) has emerged as a promisingsemiconductor for next generation integrated circuits (IC) and photonics, especiallyin flexible and ultra-thin electronic and photonic devices. With layer numbers of> 20 to 1, the electronic energy band gap of BP covers the range from 0.3 (bulk) to2 eV (single-layer), which can fill the gap between graphene and transition metaldi-chalcogenides (TMDCS). It is necessary to prepare uniform, large scale and crystallinefew-layer BP for industry applications. We investigated thinning rates of BP at different temperatures so that the userscan control the time of heating and have the ability to monitor the thickness ofBP during heating processes. Identification of crystallographic orientation (CO)of BP by Raman Spectroscopy is applied, which enables the Raman intensity ratiosbetween BP and substrates to be only thickness-dependent. This ratio can beused as a non-contact optical method to determine the actual thickness of BP duringpreparation, which is crucial to determine the end point of the thinning process.In this thesis work, we first reported the layer-by-layer sublimation of BP below600 K, which was observed by optical color changes; secondly, we investigated thethinning rates of BP at 500 K and 550 K to be 0.2 nm / min 500 K and 1.5nm / min at 550 K; thirdly, we investigated the effective determination of CO of BPand underlying Si by polarized Raman Spectroscopy with excitation wavelength of441.6 nm; fourthly, we investigated the thickness-dependent Raman peak intensity ratio Si/ A2g at a fixed CO, which can be used as an indicator of the thickness of BP;lastly, we presented the successful and repeatable preparation of large crystalline 2to 4 -layer BP. This work is the first study available to use the sublimation thinning as a controllablemethod to prepare large, uniform and crystalline BP down to 2-4 atomiclayers. This work is the first study available on developing an all-Raman methodin identifying the CO of BP, determining the in-situ and ex-situ thickness and confirmingthe crystallinity and uniformity of prepared BP.

View record

Stress engineering with silicon nitride stressors for Ge-on-Si lasers (2017)

Silicon compatible lasers are in great need for applications such as on-chip and short-reach optical interconnects. Although InAs/GaAs quantum dot lasers monolithically grown on Si have been realized and are well-performed, due to material contamination issues, it is time and cost intensive for those III-V materials to enter mainstream Si processing facilities. Germanium(Ge)-on-Silicon(Si) laser is promising as a solution to solve the Si-compatible laser problem as it is compatible with Si processing. So far, the main problems in Ge lasers are that they have a high threshold current density and low efficiency. Laser structure designs with top and side silicon nitride stressors were proposed in this work and shown to be effective in reducing the threshold current (Ith) and improving the wall-plug efficiency (ηwp) of Ge-on-Si lasers. Side stressors turned out to be a more efficient way to increase ηwp than using the top and side stressors together. With the side stressors and geometry optimizations, a maximum ηwp of 34.8% and an Ith of 36 mA (Jth of 27 kA/cm²) were achieved with a defect limited carrier lifetime (??,?) of 1 ns. With ??,? being 10 ?? , an Ith of 4 mA (Jth of 3 kA/cm²) and a ηwp of 43.8% were achieved. These are tremendous improvements from cases without any stressors. Compared to other stress introduction methods, such design is much more suitable for Ge laser structure implementation. These results provide a strong support to the Ge-on-Si laser technology and create an effective way to improve the Ge laser performance.

View record

Study of Silicon-Germanium Interdiffusion with Highly N-Type Doping (2016)

Silicon photonics has emerged as an effective solution to overcome the wiring limit imposed on electronic device (e.g. transistors) density and performance with continued scaling. In the past few decades, researchers all over the world have invested extensive effort on finding solutions to a Si-compatible lasing material system. Recently, Ge-on-Si lasers were demonstrated as promising candidates. Heavy n-type doping in Ge is the key technique to realize Ge lasing. However, Si-Ge interdiffusion during high-temperature growth or fabrication steps changes the distribution of Ge fraction and increases atomic intermixing, which degrades the device performance. Studies on the Si-Ge interdiffusion with high Ge fraction and P doping effects are not available.The subject is of technical significance for the structure, doping and process design of Ge-on-Si lasers and Ge based MOSFET. In this work, Si-Ge interdiffusion under high n-type doping was investigated both by experiments and by theoretical analysis: 1)Si–Ge interdiffusion with different P doping configurations was investigated. Significant interdiffusion happened when the Ge layer was doped with P at 10¹⁹ cm-³ after defect annealing, which resulted in a SiGe-alloy region at the Si-Ge interface. The thickness of this SiGe alloy was more than 150 nm. With high P-doped Ge, Si–Ge interdiffusivity is enhanced 10–20 times in the XGe > 0.7 region compared with the control sample without P doping. The phenomenon is attributed to the Fermi-level effect. Due to the high P concentration peak in the Si-Ge interdiffusion region, the concentration of negatively charged vacancy was greatly increased and thus the interdiffusivity of Si–Ge. Next, the impact of the Fermi-level effect on Si-Ge interdiffusion was further investigated by theoretical modeling. 2) Ge/Si0.25Ge0.75/Ge multilayered structures with no P doping and high P doping were investigated. A model of Si-Ge interdiffusion under high n-type doping was proposed to describe the impact of the Fermi-level effect. By fitting to the SIMS data from experiments with different anneal temperatures, it was found out that the Fermi-enhancement factor of Si-Ge interdiffusion was quadratically dependent on the ratio of electron concentration over intrinsic electron concentration (n/ni). This suggests that for Ge fractions from 0.75 to 1 under high n-type doping, Si-Ge interdiffusion is dominated by vacancies with double negative charge (V²-). This is the first work on the quantitative modeling of Si-Ge interdiffusion with high n-type doping.

View record

Study of Near-Surface Stresses in Silicon around Through Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations (2015)

Three-dimensional (3-D) integration has emerged as an effective solution to overcome the wiring limit imposed on device density and performance with continued scaling. Through silicon vias (TSVs), which provides interconnection between stacked chips, are essential for the 3-D integration. However, due to the large mismatch of the thermal expansion coefficients (CTEs) between via-filling material (Cu) and Si, thermal stresses induced during processing can result in undesirable mobility shifts in devices and serious reliability problems. In this work, the near-surface stress distributions around TSV structures were studied using both experimental and numerical approaches.Stress measurements and characterizations by micro-Raman spectroscopy at elevated temperatures are conducted to study the stress origin and evolution in TSV structures. Micro-Raman spectroscopy measures a combination of tensile and compressive near-surface stresses in the Si around TSVs. The results show that increasing the sample temperature towards the annealing temperature of the TSV sample will reduce the near-surface stresses around the TSVs. Temperature dependent measurements reveal that the stresses near TSVs have two components: 1) pre-existing stress before via filling, and 2) CTE mismatch-induced stress. To further understand the origins of the stress fields near TSVs, various TSV structures and via-filling materials are studied.The CTE mismatch-induced stress can be simulated by finite element analysis. The results obtained from the micro-Raman measurements are compared with the simulations. In particular, the differential values between the experimental data and simulation results are extracted in order to estimate the pre-existing stresses in the TSV structures. Once the pre-iiiexisting stress component is taken into account, a good agreement between the Raman measurement and the finite element calculation is obtained.The CTE-mismatch-induced stress resulted mobility change and keep-out zone (KOZ) at elevated temperatures are also estimated. Higher temperatures are shown to reduce the CTE-mismatch-induced stress component, and result in the shrinkage of KOZs in Si. The pre-existing stress is shown to be significant in a region equal or larger than the KOZs induced by CTE-mismatch-induced stress only and should be characterized and considered in the KOZ determination and circuit design.

View record

Monolithic integration of AlGaAs distributed Bragg reflectors on virtual Ge substrates via aspect ratio trapping (2012)

Over the past two decades, researchers have devoted great efforts on Si photonics to overcome the communication bottleneck of integrated circuits. In order to realize short-reach optical interconnects, excellent performance has been achieved so far on waveguides, modulators and detectors, which use Si compatible materials (e.g. SiO₂, Si₃N₄ and SiGe) and processes. However, lasers on Si have been much more difficult to implement. Monolithically integrated vertical cavity surface emitting laser (VCSEL) on Si platforms are a suitable choice as output devices on Si, and is the long-term goal of this project. The research for this thesis work chose Ge/Si ART (aspect ratio trapping) substrates as the Si platform to overcome the material mismatch between AlGaAs/GaAs system and Si, and investigated the first and crucial step of successful VCSEL integration on Si platforms, which is the VCSEL distributed Bragg reflector (DBR) growth and characterization on Ge/Si ART substrates. Three types of samples were grown and characterized to reveal the quality of DBRs and ART substrates. The results show good quality and potential for high performance VCSEL. The ART-based DBRs have reflectance spectra comparable to those grown on conventional bulk GaAs substrates and have smooth morphology. High-resolution X-ray diffraction (HRXRD) rocking curves show that the residual stress and crystal quality of the Ge films depend on oxide trench patterns. Though GaAs-DBRs have sharper satellite peaks, ART-DBRs also show good structural quality, considering the effect of more complex substrate structure with SiO₂, Ge and strained-Ge. The main peaks’ full-width-at-half-maximum (FWHM) of ART-DBR are about twice as GaAs-DBR’s. Transmission electron microscopy (TEM) images reveal very good periodicity and uniformity that are unaffected by threading dislocations or residual strain. These results are very encouraging for the successful full VCSEL growth on these substrates and also confirm that virtual Ge substrates via the ART technique are effective Si platforms for optoelectronic integrated circuits.

View record


Membership Status

Member of G+PS
View explanation of statuses

Program Affiliations


If this is your researcher profile you can log in to the Faculty & Staff portal to update your details and provide recruitment preferences.


Read tips on applying, reference letters, statement of interest, reaching out to prospective supervisors, interviews and more in our Application Guide!